By Youn-Long Steve Lin, Chao-Yang Kao, Hung-Chih Kuo, Jian-Wen Chen
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VLSI layout for Video Coding
High definition video calls for giant compression in an effort to be transmitted or saved economically. Advances in video coding criteria from MPEG-1, MPEG-2, MPEG-4 to H.264/AVC have supplied ever expanding coding potency, on the price of significant computational complexity that could in simple terms be introduced via hugely parallel processing.
This ebook offers VLSI architectural layout and chip implementation for prime definition H.264/AVC video encoding with a whole FPGA prototype. It serves as a useful reference for someone drawn to VLSI layout for video coding.
• provides cutting-edge VLSI architectural layout and chip implementation for prime definition H.264/AVC video encoding;
• Employs hugely parallel processing to convey 1080pHD, with effective layout that may be prototyped through FPGA;
• each subsystem is gifted from typical specification, algorithmic description, layout concerns, timing making plans, block diagram to test-bench verification;
Read or Download VLSI Design for Video Coding: H.264/AVC Encoding from Standard Specification to Chip PDF
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Extra info for VLSI Design for Video Coding: H.264/AVC Encoding from Standard Specification to Chip
8. Current block pixels are still propagated through shift registers, but reference block pixels are broadcasted in both the horizontal and vertical directions. A set of N N PEs is responsible for N N region in search window, where N is the block size (N D 4 in Fig. 8). Consequently, there are totally (2SRV =N ) (2SRV =N ) sets of PEs for the whole search window. By twodirectional data broadcasting, this design further increases data-reuse ratio. Komarek and Pirsch  proposed a 2D array architecture as shown in Fig.
In the next cycle, all SADs are transferred to comparators and the minimum SADs of 41 variable-size blocks are sent to MV Generators. Finally, 41 MVs of RF0 and 41 MVs of RF1 for one current MB are generated and then transferred to the fractional motion estimator (FME). Because there are sixteen 2D PE-arrays working in parallel, the required chip size is very large. Therefore, we adopt two popular methods to reduce its hardware cost. The first is 1/2-down-sampling. The number of PEs in a 2D PE-array is reduced from 16 16 D 256 to 16 8 D 128.
We synthesize our design targeted toward a TSMC 130-nm CMOS standard cell library. 7 shows the synthesis result of our IME design. 4 Summary In this chapter, we have discussed the key points of VLSI implementation for IME and introduced some hardwired IME designs. We have also proposed a multiple(P)macroblock data-reuse scheme for FSVBSME. In this method, P current MBs perform block matching in parallel and reference pixels in the overlapping region of consecutive SWs are broadcasted and fully utilized.